1. Field of the Invention
Embodiments of the invention generally relate to a gas distribution plate assembly and method for distributing gas in a processing chamber.
2. Description of the Related Art
Liquid crystal displays or flat panels are commonly used for active matrix displays such as computer and television monitors. Plasma enhanced chemical vapor deposition (PECVD) is generally employed to deposit thin films on a substrate such as a transparent substrate for flat panel display or semiconductor wafer. PECVD is generally accomplished by introducing a precursor gas or gas mixture into a vacuum chamber that contains a substrate. The precursor gas or gas mixture is typically directed downwardly through a distribution plate situated near the top of the chamber. The precursor gas or gas mixture in the chamber is energized (e.g., excited) into a plasma by applying radio frequency (RF) power to the chamber from one or more RF sources coupled to the chamber. The excited gas or gas mixture reacts to form a layer of material on a surface of the substrate that is positioned on a temperature controlled substrate support. Volatile by-products produced during the reaction are pumped from the chamber through an exhaust system.
Flat panels processed by PECVD techniques are typically large, often exceeding 370 mm×470 mm. Large area substrates approaching and exceeding 4 square meters are envisioned in the near future. Gas distribution plates (or gas diffuser plates) utilized to provide uniform process gas flow over flat panels are relatively large in size, particularly as compared to gas distribution plates utilized for 200 mm and 300 mm semiconductor wafer processing.
As the size of substrates continues to grow in the TFT-LCD industry, film thickness and film property uniformity control for large area plasma-enhanced chemical vapor deposition (PECVD) becomes an issue. TFT is one type of flat panel display. The difference of deposition rate and/or film property, such as film stress, between the center and the edge of the substrate becomes significant.
FIG. 1 illustrates a cross-sectional schematic view of a thin film transistor structure. A common TFT structure is the back channel etch (BCE) inverted staggered (or bottom gate) TFT structure shown in FIG. 1. The BCE process is preferred, because the gate dielectric (silicon nitride), and the intrinsic as well as n+ doped amorphous silicon films can be deposited in the same PECVD pump-down run. The BCE process shown here involves only 5 patterning masks. The substrate 101 may comprise a material that is essentially optically transparent in the visible spectrum, such as, for example, glass or clear plastic. The substrate may be of varying shapes or dimensions. Typically, for TFT applications, the substrate is a glass substrate with a surface area greater than about 500 mm2. A gate electrode layer 102 is formed on the substrate 101. The gate electrode layer 102 comprises an electrically conductive layer that controls the movement of charge carriers within the TFT. The gate electrode layer 102 may comprise a metal such as, for example, aluminum (Al), tungsten (W), chromium (Cr), tantalum (Ta), or combinations thereof, among others. The gate electrode layer 102 may be formed using conventional deposition, lithography and etching techniques. Between the substrate 101 and the gate electrode layer 102, there may be an optional insulating material, for example, such as silicon dioxide (SiO2) or silicon nitride (SiN), which may also be formed using an embodiment of a PECVD system described herein. The gate electrode layer 102 is then lithographically patterned and etched using conventional techniques to define the gate electrode.
A gate dielectric layer 103 is formed on the gate electrode layer 102. The gate dielectric layer 103 may be silicon dioxide (SiO2), silicon oxynitride (SiON), or SiN, deposited using an embodiment of a PECVD system described in this invention. The gate dielectric layer 103 may be formed to a thickness in the range of about 100 Å to about 6000 Å.
A bulk semiconductor layer 104 is formed on the gate dielectric layer 103. The bulk semiconductor layer 104 may comprise polycrystalline silicon (polysilicon) or amorphous silicon (α-Si), which could be deposited using an embodiment of a PECVD system described herein or other conventional methods known to the art. Bulk semiconductor layer 104 may be deposited to a thickness in the range of about 100 Å to about 3000 Å. A doped semiconductor layer 105 is formed on top of the semiconductor layer 104. The doped semiconductor layer 105 may comprise n-type (n+) or p-type (p+) doped polycrystalline (polysilicon) or amorphous silicon (α-Si), which could be deposited using an embodiment of a PECVD system described herein or other conventional methods known to the art. Doped semiconductor layer 105 may be deposited to a thickness within a range of about 100 Å to about 3000 Å. An example of the doped semiconductor layer 105 is n+ doped α-Si film. The bulk semiconductor layer 104 and the doped semiconductor layer 105 are lithographically patterned and etched using conventional techniques to define a mesa of these two films over the gate dielectric insulator, which also serves as storage capacitor dielectric. The doped semiconductor layer 105 directly contacts portions of the bulk semiconductor layer 104, forming a semiconductor junction.
A conductive layer 106 is then deposited on the exposed surface. The conductive layer 106 may comprise a metal such as, for example, aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), and combinations thereof, among others. The conductive layer 106 may be formed using conventional deposition techniques. Both the conductive layer 106 and the doped semiconductor layer 105 may be lithographically patterned to define source and drain contacts of the TFT. Afterwards, a passivation layer 107 may be deposited. Passivation layer 107 conformably coats exposed surfaces. The passivation layer 107 is generally an insulator and may comprise, for example, SiO2 or SiN. The passivation layer 107 may be formed using, for example, PECVD or other conventional methods known to the art. The passivation layer 107 may be deposited to a thickness in the range of about 1000 Å to about 5000 Å. The passivation layer 107 is then lithographically patterned and etched using conventional techniques to open contact holes in the passivation layer.
A transparent conductor layer 108 is then deposited and patterned to make contacts with the conductive layer 106. The transparent conductor layer 108 comprises a material that is essentially optically transparent in the visible spectrum and is electrically conductive. Transparent conductor layer 108 may comprise, for example, indium tin oxide (ITO) or zinc oxide, among others. Patterning of the transparent conductive layer 108 is accomplished by conventional lithographical and etching techniques.
The doped or un-doped (intrinsic) amorphous silicon (α-Si), SiO2, SiON and SiN films used in liquid crystal displays (or flat panels) may all be deposited using an embodiment of a plasma enhanced chemical vapor deposition (PECVD) system described in this invention. The TFT structure described here is merely used as an example.
As the size of substrates continues to grow in the TFT-LCD industry, especially when the substrate size is at least about 1000 mm by about 1200 mm (or about 1,200,000 mm2), film thickness and property uniformity for large area plasma-enhanced chemical vapor deposition (PECVD) becomes more problematic. Examples of noticeable uniformity problems include higher deposition rates and more compressive films in the central area of large substrates for some high deposition rate SiN and α-Si films. The thickness uniformity across the substrate appears “dome shaped”, or “center thick”, with the film in the center region thicker than the edge region. Larger substrates have worse center thick uniformity issues.
Therefore, there is a need for an improved gas distribution plate assembly that improves the uniformity of film deposition thickness and film properties for thin films, particularly SiN and α-Si, that are deposited on large substrates in PECVD chambers.